SOI means silicon on insulator. In SOI technique, the speed of silicon on insulator (SOI) devices is significantly improved compared to traditional bulk silicon devices, owing to reduced source and drain parasitic capacitance. Other advantages of SOI devices include improved shot-channel effect, latch-up prevention, and simpler device manufacturing. SOI devices also demonstrate high speed, low power consumption, high integration density, and high reliability. As a result, SOI has become one of the mainstream IC technologies.
However, the buried oxide layer (BOX) in a SOI structure presents two major challenges to a SOI device's performance and reliability. The first issue is the floating body charge effect and self-heating effects in SOI devices, which can lead to the devices performance degeneration and serious influences on the device reliability. With the size of the device continuing to shrink, the negative influence will be more prominent, thus greatly limiting the promotion of SOI technique. In this case, the buried oxide layer in a SOI device isolates the body region from the device, and charges generated from impact ionization cannot be quickly released. As a result, SOI devices have a tendency to accumulate charges and float electrically. In addition, the buried oxide layer in a SOI device has relatively low thermal conductivity which results in device self-heating. When the SOI device works, the buried oxide layer has high thermal resistance, and the device temperature is too high, thus affecting the device performance.
Recently a number of new device structures have been proposed to overcome the above problems, such as a SON (Silicon On Nothing) device and a DSOI (Drain/source on Insulator) device. U.S. Pat. No. 7,361,956 discloses a partially insulated field effect transistor, which has the top semiconductor layer connecting to the top surface of the bottom semiconductor layer. The connection eliminates the SOI floating body effects, and at the same time, reduces heat generated during the device operation. In addition, the source and drain parasitic capacitance is decreased, because there is a buried gap between the top and bottom semiconductor layers, where the source and drain regions are located. However, the device's manufacture process is very complicated. The process starts from opening a window from the top semiconductor layer, through the channel region, all the way to the bottom semiconductor layer, and then filling the window with specific semiconductor materials. The level of complexity in this process hinders continued device shrinking in the future.